Role: Design Verification Engineer
Location: Bay Area CA OR Austin TX Onsite
Position Type: 12 Months Contract
Mandatory: Exprs AXI/AMBA
Key Responsibilities:
Rich experience in constructing highly scalability configurability and reusability DV/Performance verification environment.
Experience in ASIC design/verification related field in IP Subsystem or SOC level
Experience in writing System Verilog and/or System C models for simulation
Working experience in writing UVM models checkers and stimulus constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus
Compose test plan and validation vectors to ensure functional completeness
Experience with design for verification (assertionbased design strategies code coverage functional coverage test plan gatelevel simulation backannotation etc.)
Versatile in any one of the highlevel verification flows such as SV UVM C etc. as well as knowledge of industry standard tools for verification
Excellent communication skills (both written and oral)
Strong problemsolving skills
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